LMP91000SDX【PDF 18/24 页】SPECIALTY ANALOG CIRCUIT, PDSO14

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Sheet目录39250

14页 15页 16页 17页 [18页]19页 20页 21页 22页

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

ESD Tolerance (Note 2)

Human Body Model

2kV

Charge-Device Model

1kV

Machine Model

200V

Voltage between any two pins

6.0V

Current through VDD or VSS

50mA

Current sunk and sourced by CE pin

10mA

Current out of other pins(Note 3)

5mA

Storage Temperature Range

-65°C to 150°C

Junction Temperature (Note 4)

150°C

For soldering specifications:

see product folder at www.national.com and

www.national.com/ms/MS/MS-SOLDERING.pdf

Operating Ratings (Note 1)

Supply Voltage V

S=(VDD - AGND)

2.7V to 5.25V

Temperature Range (Note 4)

-40°C to 85°C

Package Thermal Resistance (Note 4)

14-Pin LLP (

JA)

44 °C/W

Electrical Characteristics (Note 5)

Unless otherwise specified, all limits guaranteed for T

A = 25°C, VS=(VDD – AGND), VS=3.3V and AGND = DGND =0V,

VREF= 2.5V, Internal Zero= 20% VREF. Boldface limits apply at the temperature extremes.

Symbol

Parameter

Conditions

Min

(Note 7)

Typ

(Note 6)

Max

(Note 7)

Units

Power Supply Specification

Supply Current

3-lead amperometric cell mode

MODECN = 0x03

13.5

Standby mode

MODECN = 0x02

6.5

Temperature Measurement mode with TIA OFF

MODECN = 0x06

11.4

13.5

Temperature Measurement mode with TIA ON

MODECN = 0x07

14.9

2-lead ground referred galvanic cell mode

VREF=1.5V

MODECN = 0x01

6.2

Deep Sleep mode

MODECN = 0x00

0.6

0.85

Potentiostat

Bias_RW

Bias Programming range

(differential voltage between RE

pin and WE pin)

Percentage of voltage referred to VREF or VDD

±24

Bias Programming Resolution

First two smallest step

±1

All other steps

±2

Input bias current at RE pin

VDD=2.7V;

Internal Zero 50% VDD

-90

-800

800

VDD=5.25V;

Internal Zero 50% VDD

-90

-900

900

Minimum operating current

capability

sink

750

source

750

Minimum charging capability

(Note 9)

sink

source

AOL_A1

Open loop voltage gain of

control loop op amp (A1)

300mV

≤VCE≤Vs-300mV;

-750A

≤ICE≤750A

104

120

en_RW

Low Frequency integrated noise

between RE pin and WE pin

0.1Hz to 10Hz, Zero Bias

(Note 10)

3.4

Vpp

0.1Hz to 10Hz, with Bias

(Note 10, Note 11)

5.1

www.national.com

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